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19-1083; Rev 1; 8/96
+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down
_______________General Description
The MAX114/MAX118 are microprocessor-compatible, 8-bit, 4-channel and 8-channel analog-to-digital converters (ADCs). They operate from a single +5V supply and use a half-flash technique to achieve a 660ns conversion time (1Msps). A power-down (PWRDN) pin reduces current consumption typically to 1A. The devices return from power-down mode to normal operating mode in less than 200ns, allowing large supplycurrent reductions in burst-mode applications (in burst mode, the ADC wakes up from a low-power state at specified intervals to sample the analog input signals). Both converters include a track/hold, enabling the ADC to digitize fast analog signals. Microprocessor (P) interfaces are simplified because the ADC can appear as a memory location or I/O port without external interface logic. The data outputs use latched, three-state buffer circuitry for direct connection to an 8-bit parallel P data bus or system input port. The MAX114/MAX118 input/reference configuration enables ratiometric operation. The 4-channel MAX114 is available in a 24-pin DIP or SSOP. The 8-channel MAX118 is available in a 28-pin DIP or SSOP. For +3V applications, refer to the MAX113/MAX117 data sheet.
____________________________Features
o Single +5V Supply Operation o 4 (MAX114) or 8 (MAX118) Analog Input Channels o Low Power: 40mW (operating mode) 5W (power-down mode) o Total Unadjusted Error 1LSB o Fast Conversion Time: 660ns per Channel o No External Clock Required o Internal Track/Hold o 1MHz Full-Power Bandwidth o Internally Connected 8th Channel Monitors Reference Voltage (MAX118)
MAX114/MAX118
______________Ordering Information
PART MAX114CNG MAX114CAG MAX114C/D MAX114ENG MAX114EAG MAX114MRG TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 24 Narrow Plastic DIP 24 SSOP Dice* 24 Narrow Plastic DIP 24 SSOP 24 Narrow CERDIP**
________________________Applications
High-Speed DSP Portable Equipment Remote Data Acquisition Communications Systems
Ordering Information continued on last page. *Dice are specified at TA = +25C, DC parameters only. **Contact factory for availability. Pin Configurations appear on last page.
_________________________________________________________Functional Diagram
REF+ D7 D6 D5 D4
*IN8 *IN7 *IN6 *IN5 IN4 IN3 IN2 IN1 MUX
4-BIT FLASH ADC (4MSBs)
REF+ 16
4-BIT DAC
THREESTATE OUTPUT DRIVERS D3 D2 D1 D0
4-BIT FLASH ADC (4LSBs) TIMING AND CONTROL
ADDRESS LATCH DECODE
MAX114/MAX118
A0 * MAX118 ONLY A1 A2 REFRD CS PWRDN MODE WR/RDY INT
________________________________________________________________ Maxim Integrated Products
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down MAX114/MAX118
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +7V Digital Input Voltage to GND ......................-0.3V to (VDD + 0.3V) Digital Output Voltage to GND ...................-0.3V to (VDD + 0.3V) REF+ to GND..............................................-0.3V to (VDD + 0.3V) REF- to GND...............................................-0.3V to (VDD + 0.3V) IN_ to GND .................................................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70C) 24-Pin Narrow Plastic DIP (derate 13.33mW/C above +70C)....................................1.08W 24-Pin SSOP (derate 8.00mW/C above +70C)..............640mW 24-Pin Narrow CERDIP (derate 12.50mW/C above +70C).........................................1W 28-Pin Wide Plastic DIP (derate 14.29mW/C above +70C)....................................1.14W 28-Pin SSOP (derate 9.52mW/C above +70C)..............762mW 28-Pin Wide CERDIP (derate 16.67mW/C above +70C)....................................1.33W Operating Temperature Ranges MAX114/MAX118C_ _...........................................0C to +70C MAX114/MAX118E_ _ ........................................-40C to +85C MAX114/MAX118M_ _ .....................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 5%, REF+ = 5V, REF- = GND, Read Mode (MODE = GND), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER ACCURACY (Note 1) Resolution Total Unadjusted Error Differential Nonlinearity Zero-Code Error Full-Scale Error Channel-to-Channel Mismatch DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Input Full-Power Bandwidth Input Slew Rate, Tracking ANALOG INPUT Input Voltage Range Input Leakage Current Input Capacitance REFERENCE INPUT Reference Resistance REF+ Input Voltage Range REF- Input Voltage Range RREF 1 VREFGND 2 4 VDD VREF+ k V V VIN_ IIN_ CIN_ GND < VIN_ < VDD 32 VREFVREF+ 3 V A pF SINAD THD SFDR MAX11_C/E, fSAMPLE = 1MHz, fIN_ = 195.8kHz MAX11_M, fSAMPLE = 740kHz, fIN_ = 195.7kHz MAX11_C/E, fSAMPLE = 1MHz, fIN_ = 195.8kHz MAX11_M, fSAMPLE = 740kHz, fIN_= 195.7kHz MAX11_C/E, fSAMPLE = 1MHz, fIN_ = 195.8kHz MAX11_M, fSAMPLE = 740kHz, fIN_ = 195.7kHz VIN_ = 5Vp-p 3.1 50 50 1 15 45 45 -50 -50 dB dB dB MHz V/s N TUE DNL No-missing-codes guaranteed 8 1 1 1 1 1/4 Bits LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%, REF+ = 5V, REF- = GND, Read Mode (MODE = GND), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER LOGIC INPUTS Input High Voltage Input Low Voltage VINH VINL CS, WR, RD, PWRDN, A0, A1, A2 MODE CS, WR, RD, PWRDN, A0, A1, A2 MODE CS, RD, PWRDN, A0, A1, A2 Input High Current Input Low Current Input Capacitance (Note 2) LOGIC OUTPUTS Output Low Voltage Output High Voltage Three-State Current Three-State Capacitance (Note 2) POWER REQUIREMENTS Supply Voltage VDD Supply Current Power-Down VDD Current Power-Supply Rejection PSR VDD IDD CS = RD = 0V, PWRDN = VDD MAX11_C MAX11_E/M 4.75 8 8 1 1/16 5.25 15 20 10 1/4 V mA A LSB VOL VOH ILKG COUT ISINK = 1.6mA, INT, D0-D7 RDY, ISINK = 2.6mA ISOURCE = 360A, INT, D0-D7 D0-D7, RDY, digital outputs = 0V to VDD D0-D7, RDY 5 4 3 8 0.4 0.4 V V A pF IINH IINL CIN WR MODE CS, WR, RD, PWRDN, MODE, A0, A1, A2 CS, WR, RD, PWRDN, MODE, A0, A1, A2 5 50 2.4 3.5 0.8 1.5 1 3 200 1 8 A pF A V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX114/MAX118
CS = RD = VDD, PWRDN = 0V (Note 3) VDD = 4.75V to 5.25V, VREF = 4.75V
Note 2: Guaranteed by design. Note 3: Power-down current increases if logic inputs are not driven to GND or VDD.
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down MAX114/MAX118
TIMING CHARACTERISTICS
(VDD = +4.75V, TA = +25C, unless otherwise noted.) (Note 4) PARAMETER Conversion Time (WR-RD Mode) Conversion Time (RD Mode) Power-Up Time CS to RD, WR Setup Time CS to RD, WR Hold Time CS to RDY Delay Data-Access Time (RD Mode) RD to INT Delay (RD Mode) Data Hold Time Minimum Acquisition Time WR Pulse Width Delay Between WR and RD Pulses RD Pulse Width (WR-RD Mode) Data-Access Time (WR-RD Mode) RD to INT Delay WR to INT Delay RD Pulse Width (WR-RD Mode) Data-Access Time (WR-RD Mode) WR to INT Delay Data-Access Time after INT Multiplexer Address Hold Time Note 4: Note 5: Note 6: Note 7: SYMBOL CONDITIONS tRD < tINTL, (Note 5) CL = 20pF CL = 100pF TA = +25C ALL GRADES MIN tCWR tCRD tUP tCSS tCSH tRDY tACC0 tINTH tDH tACQ tWR tRD tREAD1 tACC1 tRI tINTL tREAD2 tACC2 tIHWR tID tAH CL = 50pF tRD > tINTL, determined by tACC2 tRD > tINTL, CL = 100pF (Note 5) Pipelined mode, CL = 50pF Pipelined mode, CL = 100pF 30 65 90 80 45 35 380 tRD < tINTL, determined by tACC1 tRD < tINTL, CL = 100pF (Note 5) CL = 50pF, RL = 5.1k to VDD CL = 100pF (Note 5) CL = 50pF (Note 6) (Note 7) 160 0.25 0.25 160 185 150 500 75 110 100 60 40 10 50 0 0 70 tCRD + 50 80 60 185 0.28 0.35 205 235 185 610 85 130 120 70 10 TYP MAX 660 685 700 320 0 0 85 tCRD + 65 85 70 260 0.4 0.45 240 275 220 700 10 TA = TMIN to TMAX MAX11_C/E MAX11_M MIN MAX MIN MAX 865 875 370 0 0 100 tCRD + 75 90 80 1125 975 520 UNITS
ns ns ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns
Input control signals are specified with tr = tf = 5ns, 10% to 90% of 5V, and timed from a voltage level of 1.6V. See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.8V or 2.4V. See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V. Also defined as the Minimum Address-Valid to Convert-Start Time.
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down
__________________________________________Typical Operating Characteristics
(VDD = +5V, TA = +25C, unless otherwise noted.)
CONVERSION TIME vs. AMBIENT TEMPERATURE
MAX114/118-01
MAX114/MAX118
tCRD (NORMALIZED TO VALUE AT VDD = +5V, +25C)
EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY (WR-RD MODE)
MAX114/118-02
1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -60 -20 20 60 100 VDD = +5V VDD = +5.25V VDD = +4.75V
8.0 EFFECTIVE NUMBER OF BITS
7.5
7.0
6.5 fSAMPLE = 1MHz VIN = 4.96Vp-p 6.0 1k 10k 100k 1M
140
TEMPERATURE (C)
INPUT FREQUENCY (Hz)
AVERAGE POWER CONSUMPTION vs. SAMPLING RATE USING PWRDN
MAX114/118-03
SIGNAL-TO-NOISE RATIO
MAX114/118-04
50
0 VDD = 4.75V INPUT FREQUENCY = 195.8ksps VIN = 4.72Vp-p SAMPLE FREQUENCY = 1MHz SNR = 48.2dB
POWER DISSIPATION (mW)
40
-20 RATIO (dB)
30
-40
20
-60
10 0 1k 10k 100k 1M SAMPLING RATE (CONVERSIONS/SEC)
-80
-100
0
100
200
300
400
500
FREQUENCY (kHz)
TOTAL UNADJUSTED ERROR vs. POWER-UP TIME
MAX114/118-06
SUPPLY CURRENT vs. TEMPERATURE (EXCLUDING REFERENCE CURRENT)
MAX114/118-08
6 5 4 TUE (LSB) 3 2 1 0 75 100 125 150 175 200 225
12 10 SUPPLY CURRENT (mA) 8 6 4 2 0
250
-60
-20
20
60
100
140
POWER-UP TIME, tUP (ns)
TEMPERATURE (C)
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down MAX114/MAX118
______________________________________________________________Pin Description
PIN MAX114 -- -- 1 2 3 4 5 6 7, 8, 9 10 11 12 13 14 15 16 17, 18, 19 20 -- 21 22 23 24 -- MAX118 1 2 3 4 5 6 7 8 9, 10, 11 12 13 14 15 16 17 18 19, 20, 21 22 23 24 25 26 27 28 NAME IN6 IN5 IN4 IN3 IN2 IN1 MODE D0 D1, D2, D3 RD INT GND REFREF+ WR/RDY CS D4, D5, D6 D7 A2 A1 A0 PWRDN VDD IN7 Analog Input Channel 6 Analog Input Channel 5 Analog Input Channel 4 Analog Input Channel 3 Analog Input Channel 2 Analog Input Channel 1 Mode Selection Input. Internally pulled low with a 50A current source. MODE = 0 activates read mode; MODE = 1 activates write-read mode (see Digital Interface Section). Three-State Data Output (LSB) Three-State Data Outputs Read Input. RD must be low to access data (see Digital Interface section). Interrupt Output. INT goes low to indicate end of conversion (see Digital Interface section). Ground Lower Limit of Reference Span. REF- sets the zero-code voltage. Range is GND VREF- < VREF+. Upper Limit of Reference Span. REF+ sets the full-scale input voltage. Range is VREF< VREF+ VDD. Internally hard-wired to IN8 (Table 1). Write-Control Input/Ready-Status Output (see Digital Interface section) Chip-Select Input. CS must be low for the device to recognize WR or RD inputs. Three-State Data Outputs Three-State Data Output (MSB) Multiplexer Channel Address Input (MSB) Multiplexer Channel Address Input Multiplexer Channel Address Input (LSB) Power-Down Input. PWRDN reduces supply current when low. Positive Supply, +5V Analog Input Channel 7 FUNCTION
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down
_______________Detailed Description
Converter Operation
The MAX114/MAX118 use a half-flash conversion technique (see Functional Diagram) in which two 4-bit flash ADC sections achieve an 8-bit result. Using 15 comparators, the flash ADC compares the unknown input voltage to the reference ladder and provides the upper four data bits. An internal digital-to-analog converter (DAC) uses the four most significant bits (MSBs) to generate both the analog result from the first flash conversion and a residue voltage that is the difference between the unknown input and the DAC voltage. The residue is then compared again with the flash comparators to obtain the lower four data bits (LSBs). An internal analog multiplexer enables the devices to read four (MAX114) or eight (MAX118) different analog voltages under microprocessor (P) control. One of the MAX118's analog channels, IN8, is internally hardwired and always reads VREF+ when selected.
Power-Down Mode
In burst-mode or low sample-rate applications, the MAX114/MAX118 can be shut down between conversions, reducing supply current to microamp levels (see Typical Operating Characteristics). A logic low on the PWRDN pin shuts the devices down, reducing supply current typically to 1A when powered from a single +5V supply. A logic high on PWRDN wakes up the MAX114/MAX118, and the selected analog input enters the track mode. The signal is fully acquired after 360ns (this includes both the power-up delay and the track/hold acquisition time), and a new conversion can be started. If the power-down feature is not required, connect PWRDN to VDD. For minimum current consumption, keep digital inputs at the supply rails in power-down mode. Refer to the Reference section for information on reducing reference current during power-down.
MAX114/MAX118
___________________Digital Interface
The MAX114/MAX118 have two basic interface modes, which are set by the MODE pin. When MODE is low, the converters are in read mode; when MODE is high, the converters are set up for write-read mode. The A0, A1, and A2 inputs control channel selection, as shown in Table 1. The address must be valid for a minimum time, tACQ, before the next conversion starts.
VDD
DATA OUTPUTS
DATA OUTPUTS
RL = 3k
RL = 3k
CL
CL
Table 1. Truth Table for Input Channel Selection
MAX114 A1 0 0 1 1 -- -- -- -- A0 0 1 0 1 -- -- -- -- A2 0 0 0 0 1 1 1 1 MAX118 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 SELECTED CHANNEL IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 (reads VREF+ if selected)
a) HIGH-Z TO VOH
b) HIGH-Z TO VOL
Figure 1. Load Circuits for Data-Access Time Test
VDD
3k DATA OUTPUTS DATA OUTPUTS
Read Mode (MODE = 0)
3k 10pF 10pF
a) VOH TO HIGH-Z
b) VOL TO HIGH-Z
Figure 2. Load Circuits for Data-Hold Time Test
In read mode, conversions and data access are controlled by the RD input (Figure 3). The comparator inputs track the analog input voltage for the duration of tACQ. Initiate a conversion by driving CS and RD low. With Ps that can be forced into a wait state, hold RD low until output data appears. The P starts the conversion, waits, and then reads data with a single read instruction.
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down MAX114/MAX118
In read mode, WR/RDY is configured as a status output (RDY), so it can drive the ready or wait input of a P. RDY is an open-collector output (no internal pull-up) that goes low after the falling edge of CS and goes high at the end of the conversion. If not used, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and returns high on the rising edge of CS or RD.
Fastest Conversion: Reading Before Delay
Figure 5 shows an external method of controlling the conversion time. The internally generated delay (tINTL) varies slightly with temperature and supply voltage, and can be overridden with RD to achieve the fastest conversion time. RD is brought low after the rising edge of WR, but before INT goes low. This completes the conversion and enables the output buffers that contain the conversion result (D0-D7). INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. The total conversion time is therefore: tWR + tRD + tACC1 = 660ns.
Write-Read Mode (MODE = 1)
Figures 4 and 5 show the operating sequence for writeread mode. The comparator inputs track the analog input voltage for the duration of tACQ. The conversion is initiated by a falling edge of WR. When WR returns high, the result of the four-MSBs flash is latched into the output buffers and the conversion of the four-LSBs flash starts. INT goes low, indicating conversion end, and the lower four data bits are latched into the output buffers. The data is then accessible after RD goes low (see Timing Characteristics). A minimum acquisition time (tACQ) is required from INT going low to the start of another conversion (WR going low). Options for reading data from the converter include using internal delay, reading before delay, and pipelined operation (discussed in the following sections).
CS tCSS WR tACQ A0-A2 tWR tAH ADDRESS VALID (N) tACQ ADDRESS VALID (N + 1) tCSS tREAD2 tRD tINTL D0-D7 tACC2 tINTH tCSH tCSH
RD INT
Using Internal Delay
The P waits for the INT output to go low before reading the data (Figure 4). INT goes low after the rising edge of WR, indicating that the conversion is complete and the result is available in the output latch. With CS low, data outputs D0-D7 can be accessed by pulling RD low. INT is then reset by the rising edge of CS or RD.
VALID DATA (N)
tDH
Figure 4. Write-Read Mode Timing (tRD > tINTL) (MODE = 1)
PWRDN CS
tUP
CS tWR tCSS tAH tCSH tRD tACQ ADDRESS VALID (N) tINTL ADDRESS VALID (N + 1) tCSS RD INT tREAD1 tRI tINTH tCSH tACQ
tCSH RD A0-A2 RDY INT tCRD D0-D7 tACCO
VALID DATA (N)
WR
tCSS ADDRESS VALID (N) tAH tACQ tRDY WITH EXTERNAL PULL-UP
tACQ A0-A2 ADDRESS VALID (N + 1) tAH tINTH tDH
D0-D7 tCWR tACC1
VALID DATA (N)
tDH
Figure 3. Read Mode Timing (MODE = 0)
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Figure 5. Write-Read Mode Timing (tRD < tINTL) (MODE = 1)
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down
Pipelined Operation
Besides the two standard write-read-mode options, pipelined operation can be achieved by connecting WR to RD (Figure 6). With CS low, driving WR and RD low initiates a conversion and concurrently reads the result of the previous conversion.
CS tCSS RD, WR tACQ A0-A2 tAH ADDRESS VALID (N) tIHWR INT tINTL tID D0-D7 OLD DATA (N - 1) NEW DATA (N) tWR tACQ ADDRESS VALID (N + 1) tCSH
MAX114/MAX118
_____________Analog Considerations
Reference
Figures 7a, 7b, and 7c show typical reference connections. The voltages at REF+ and REF- set the ADC's analog input range (see Figure 10). The voltage at REFdefines the input that produces an output code of all zeros, and the voltage at REF+ defines the input that produces an output code of all ones. The internal resistance from REF+ to REF- can be as low as 1k, and current will flow through it even when the MAX114/MAX118 are shut down. Figure 7d shows how an N-channel MOSFET can be connected to REF-
Figure 6. Pipelined Mode Timing (WR = RD) (MODE = 1)
VIN+ VIN-
IN_ GND +5V
VIN+
IN_ GND VDD MAX114 MAX118
+5V 4.7F 0.1F
MAX114 VDD MAX118
REF+ REF-
4.7F
0.1F +2.5V VINR* 0.1F
REF+ REF0.1F
* CURRENT PATH MUST STILL EXIST FROM VIN- TO GND
Figure 7a. Power Supply as Reference
Figure 7c. Input Not Referenced to GND
+5V VIN+ VIN+5V 4.7F 0.1F IN_ GND 0.1F
VDD
MAX874
VDD MAX114 MAX118 REF+
C1 3.3F
REF+
MAX114 MAX118
MX584
C1 0.1F REFPWRDN
REFN-FET* 0.1F
PWRDN * IRML2402
Figure 7b. External Reference, 4.096V Full Scale
Figure 7d. An N-channel MOSFET switches off the reference load during power-down
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down
to break this current path during power-down. The FET should have an on-resistance of less than 2 with a 5V gate drive. When REF- is switched, as in Figure 7d, a new conversion can be initiated after waiting a period of time equal to the power-up delay (tUP) plus the Nchannel FET's turn-on time. Although REF+ is frequently connected to VDD, the circuit of Figure 7d uses a low-current, low-dropout, 4.096V voltage reference: the MAX874. Since the MAX874 cannot continuously furnish enough current for the reference resistance, this circuit is intended for applications where the MAX114/MAX118 are normally in standby and are turned on in order to make measurements at intervals greater than 65s. C1 (the capacitor connected to REF+) is slowly charged by the MAX874 during the standby period, and furnishes the reference current during the short measurement period. C1's 3.3F value ensures a voltage drop of less than 1/2LSB when performing four to eight successive conversions. Larger capacitors reduce the error still further. Use ceramic or tantalum capacitors for C1.
MAX114/MAX118
Analog Inputs
Figure 8 shows the equivalent circuit of the MAX114/ MAX118 input. When a conversion starts and WR is low, V IN_ is connected to sixteen 0.6pF capacitors. During this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches. In addition, about 22pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 9). As source impedance increases, the capacitors take longer to charge. The typical 32pF input capacitance allows source resistance as high as 800 without setup problems. For larger resistances, the acquisition time (tACQ) must be increased. Internal protection diodes, which clamp the analog input to VDD and GND, allow the channel input pins to swing from GND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than GND by 50mV. If the analog input exceeds 50mV beyond the supplies, limit the input current to no more than 2mA, as excessive current will degrade the conversion accuracy of the on channel.
Initial Power-Up
When power is first applied, perform a conversion to initialize the MAX114/MAX118. Disregard the output data.
Bypassing
Use a 4.7F electrolytic in parallel with a 0.1F ceramic capacitor to bypass VDD to GND. Minimize capacitor lead lengths. Bypass the reference inputs with 0.1F capacitors, as shown in Figures 7a, 7b, and 7c.
Track/Hold The track/hold enters hold mode when a conversion starts (RD low or WR low). INT goes low at the end of the conversion, at which point the track/hold enters track mode. The next conversion can start after the minimum acquisition time, tACQ.
MUX VIN2 RIN
MAX114 MAX118
RON T/H
RIN VIN_
VIN
2k
. . .
22pF
10pF
MAX114 MAX118
Figure 8. Equivalent Input Circuit
10
Figure 9. RC Network Equivalent Input Model
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down
Transfer Function Figure 10 shows the MAX114/MAX118's nominal transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary with 1LSB = (VREF+ - VREF-) / 256.
MAX114/MAX118
OUTPUT CODE 11111111 11111110 11111101
FULL-SCALE TRANSITION
Conversion Rate
The maximum sampling rate (fMAX) for the MAX114/ MAX118 is achieved in write-read mode (tRD < tINTL), and is calculated as follows: 1 fMAX = t WR + t RD + tRI + t ACQ fMAX = 1 250ns + 250ns + 150ns + 160ns
1LSB =
VREF+ - VREF256
00000011 00000010 00000001 VREF+ 1 2 3 INPUT VOLTAGE (LSBs) FS FS - 1LSB
fMAX = 1.23MHz where tWR = the write pulse width, t RD = the delay between write and read pulses, tRI = RD to INT delay, and tACQ = minimum acquisition time.
00000000 VREF-
Figure 10. Transfer Function
Signal-to-Noise Ratio and Effective Number of Bits
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to all other ADC output signals. The output spectrum is limited to frequencies above DC and below one-half the ADC sample rate. The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADC's resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 50dB. The FFT Plot (see Typical Operating Characteristics) shows the result of sampling a pure 195.8kHz sinusoid at a 1MHz rate. This FFT plot of the output shows the output level in various spectral bands. The effective resolution (or "effective number of bits") the ADC provides can be measured by transposing the equation that converts resolution to SNR: N = (SINAD 1.76) / 6.02 (see Typical Operating Characteristics).
band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as: 2 2 2 2 V2 + V3 + V4 + ...VN THD = 20log V1
where V1 is the fundamental RMS amplitude, and V2 through VN are the amplitudes of the 2nd through Nth harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADC's noise floor. See the Signal-toNoise Ratio graph in Typical Operating Characteristics.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequency
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+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1A Power-Down MAX114/MAX118
__Ordering Information (continued)
PART MAX118CPI MAX118CAI MAX118C/D MAX118EPI MAX118EAI MAX118MJI TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 28 Wide Plastic DIP 28 SSOP Dice* 28 Wide Plastic DIP 28 SSOP 28 Wide CERDIP**
___________________Chip Information
TRANSISTOR COUNT: 2011
*Dice are specified at TA = +25C, DC parameters only. **Contact factory for availability.
__________________________________________________________Pin Configurations
TOP VIEW
IN6 1 IN4 1 IN3 2 IN2 3 IN1 4 MODE 5 D0 6 D1 7 D2 8 D3 9 RD 10 INT 11 GND 12 24 VDD 23 PWRDN 22 A0 21 A1 IN5 2 IN4 3 IN3 4 IN2 5 IN1 6 MODE 7 D0 8 D1 9 D2 10 D3 11 RD 12 INT 13 GND 14 28 IN7 27 VDD 26 PWRDN 25 A0
MAX114
20 D7 19 D6 18 D5 17 D4 16 CS 15 WR/RDY 14 REF+ 13 REF-
MAX118
24 A1 23 A2 22 D7 21 D6 20 D5 19 D4 18 CS 17 WR/RDY 16 REF+ 15 REF-
DIP/SSOP
DIP/SSOP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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